The present invention relates generally to semiconductor devices, and more particularly to dynamic random access memory (DRAM) storage cells and arrays.
As the complexity and power of computing systems increases, the amount of memory required for systems has also increased. This has resulted in the drive for semiconductor memory devices of increased storage capacity. At the same time, the desire for more efficient manufacturing and more compact electronic devices, has led to the competing interest of shrinking semiconductor memory devices to as small a size as possible.
A common type of semiconductor memory device is the dynamic random access memory (DRAM). DRAMs typically include a large number (millions or thousands) of memory cells, each of which can store at least one bit of data. The memory cells are usually arranged into an array configuration of rows and columns. Because the primary function of DRAM is to store data, the DRAM array makes up the majority of the area on a DRAM. Thus, any reduction in the size of a memory cell translates into reduced array size, and hence a smaller overall DRAM. Furthermore, a smaller memory cell allows more information to be stored in a given amount of area, leading to larger capacity DRAMs.
One reason for the increase in system computing power is the faster speeds at which such systems operate. For this reason, it is also desirable to provide a DRAM that has a fast operating speed, in order to provide data at a sufficient rate to a system. Another important aspect of DRAM operation arises from the fact that DRAMs are being used more often in battery operated applications, such as laptop computers. Thus, the rate of power consumption is an important feature of a DRAM. Lower power DRAMs can contribute to longer battery lifetimes in battery operated systems.
A typical DRAM array includes memory cells within the same row being commonly coupled to a word line, while memory cells within the same column are commonly coupled to a bit line. The data stored within the memory cells can be accessed according to various DRAM operations such as read operations, write operations and refresh operations. A memory cell access operation will usually begin with the application of an external memory address, resulting in the activation of a word line. Once activated, the word line couples the data stored within its respective row to the bit lines of the array.
The coupling of memory cells to bit lines results in differential voltage signals appearing on the bit lines (or bit line pairs). The differential signals are relatively small, and so must be amplified (usually by a sense amplifier), resulting in amplified data signals on the bit lines. The applied memory address also activates column decoder circuits, which connect a given group of bit lines to input/output circuits. Commonly, the memory address is multiplexed, with a row address being applied initially to select a word line, and a column address being applied subsequently to select the group of bit lines.
The typical DRAM memory cell stores data by placing charge on, or removing charge from, a storage capacitor. Once a storage capacitor has been initially charged, over time, the amount of charge will be reduced by way of a leakage current. Thus, it is important for the DRAM to restore the charge on the capacitor before the amount of charge falls below a critical level, due to leakage mechanisms. Restoration of charge is accomplished with a refresh operation.
The critical level of charge for a storage capacitor arises out of the minimum sensitivity of the DRAM sense amplifiers. The storage capacitor must have enough charge to create a sufficient differential voltage on the bit lines for the sense amplifier to reliably sense. The time needed before the charge on the capacitor falls below the critical level is commonly referred to as the maximum xe2x80x9cpausexe2x80x9d period. A DRAM must perform a refresh operation on every row in the device before that row experiences the maximum xe2x80x9cpausexe2x80x9d period, without having its cells refreshed by way of a refresh operation, read operation, or a write operation.
The refreshing operation of a DRAM consumes a relatively large amount of power. Minimizing the power used for refresh is thus a desirable goal. One way to reduce refresh power consumption is to reduce the rate of charge leakage from the storage capacitor. This increases the maximum pause period, allowing refresh operation to occur with less frequency.
Referring now to FIG. 1, a prior DRAM array is set forth and designated by the general reference character 100. The DRAM array 100 is arranged as an nxc3x97m array, having n rows coupled to n word lines (WL0-WLn) and m sets of bit line pairs (BL0, BL0_-BLm, BLm_). A memory cell is formed where a word line intersects a bit line pair. The memory cells are designated as M00-Mnm, where the first digit following the xe2x80x9cMxe2x80x9d represents the physical row of the memory cell""s location, and the second digit represents the physical column of the memory cell""s location. For example, M00 is the memory cell located at the intersection of WL0 and bit line pair BL0/BL0_. Each memory cell (M00-Mnm) contains a pass transistor (shown as n-channel MOSFETs Q00-Qnm) and a storage capacitor (shown as C00-Cnm).
The word lines of the DRAM array 100 are driven by a word line driver bank 102 coupled to the word lines (WL0-WLn). In addition, a sense amplifier bank 104 is coupled to the bit line pairs (BL0, BL0_-BLm, BLm_). The word line driver bank 102 is separated into n separate word line driver circuits, shown as DRV0-DRVn. The word line driver bank 102 is responsive to a row address (not shown) in such a manner, that only one word line driver circuit (DRV0-DRVn) will drive its corresponding word line high when the row address received. For example, word line driver circuit DRV0 will drive word line WL0 high when the row address value of xe2x80x9czeroxe2x80x9d is received, and word line driver circuit DRVn will drive word line WLn high when the row address value of xe2x80x9cnxe2x80x9d is received.
The sense amplifier bank 104 is separated into m separate sense amplifier circuits, shown as SA0-SAm. While all of the sense amplifiers 104 will be activated simultaneously, only selected of the sense amplifiers (SA0-SAm) will pass its sensed data to the DRAM outputs (not shown). A sense amplifier (SA0-SAm) will be selected according to the column address (not shown) applied to a column decoder (also not shown) in the DRAM.
As noted previously, data is stored in the DRAM array 100 by placing or removing charge from the storage capacitors (C00-Cnm). Each memory cell (M00-Mnm) is shown to further include a storage node 106-112 formed at the junction of the source of the pass transistor (Q00-Qnm), and its associated storage capacitor (C00-Cnm). The potential at the storage node will determine the logic of the data stored within the memory cell. A memory cell (Q00-Mnm) is accessed by coupling its storage node (106-112) to its respective bit line (BL0, BL0_-BLm, BLm_).
In a write cycle, a row address is applied to the DRAM and will activate a word line. If it is assumed that a logic value xe2x80x9c1xe2x80x99 is to be written into memory cell M00, word line driver circuit DRV0 will raise word line WL0 to a high voltage level. A column address will couple write circuitry (not shown) to bit line BL0 to allow a high logic level to be written into storage cell M00. The high logic level will be stored in memory cell M00 at storage node 106 by placing charge on storage capacitor C00. In order to ensure maximum charge is placed on the storage capacitor, word line driver circuit DRV0 will raise word line WL0 to a voltage level that is at least one n-channel threshold voltage (Vtn) above the voltage level applied to bit line BL0 during the write cycle.
Once the storage node 106 reaches a high logic level, which is typically equal to the high power supply voltage (Vcc) of the DRAM array 100, the DRAM is allowed to go into a precharge state in which word line WL0 will be driven to a low logic level, for example the low power supply voltage (Vss). In this state, the storage node 106 will be isolated from the bit line BL0 as the pass transistor Q00 will be in a non-conducting state.
Because the leakage characteristics of the storage capacitor C00 and pass transistor Q00 are not ideal, once the storage node 106 becomes isolated from the bit line BL0, the charge stored on the storage capacitor C00 will leak away, and the voltage will slowly begin to fall. As noted above, in order to ensure sufficient sensing of the data signal, the charge on the storage capacitor C00 must be restored before the charge level falls below the critical level. The data may be restored during either a read operation or a refresh operation, as determined by control signals (not shown) that may be applied to the DRAM. In both cases, the data of a complete row of DRAM cells will be restored.
In order to restore the data in the row formed by word line WL0, word line driver WL0, will be activated, raising word line WL0 at least one Vtn above the DRAM array 100 high power supply voltage (Vcc). As a result, the pass transistors coupled to word line WL0 will be turned on, coupling the storage nodes of the row to their respective bit lines BL0-BLm. This will create a differential voltage across the bit line pairs (BL0, BL0_-BLm, BLm_) having a value that is dependent upon the data stored at the accessed storage nodes. In the example described above, storage node 106 has a logic level xe2x80x9c1xe2x80x9d stored on it. Thus, during a read or refresh operation, when word line WL0 is accessed, bit line BL0 will rise to a potential that is a slightly higher than the potential of bit line BL0_. Conversely, if the storage node 106 had a logic level xe2x80x9c0xe2x80x9d stored on it, the bit line BL0 would achieve a lower voltage than that of bit line BL0_.
After a differential voltage is achieved on the bit lines (BL0, BL0_-BLm, BLm_), the sense amplifier bank 104 is activated. When activated, the sense amplifiers (SA0-SAm) amplify the voltage differential on the bit lines pairs (BL0, BL0_-BLm, BLm_), to generate output signals having a full logic level (either Vcc or Vss, depending upon the logic level stored in the memory cell).
Because the pass transistors coupled to word line WL0 are still turned on when the differential voltage signals are amplified, fall logic levels will be applied to the bit line pairs (BL0, BL0_ to BLm, BLm_). Referring back to the example of memory cell M00, because the memory cell stores a logic xe2x80x9c1xe2x80x9d, sense amplifier SA0 will apply a voltage level of Vcc to bit line BL0 and a voltage of Vss to bit line BL0_. With word line WL0 at a voltage at least one Vtn above Vcc, a full Vcc level will be applied back to the storage node 106, and the voltage level on the storage node 106 will be restored. In this manner, all of the memory cells coupled to word line WL0 will have their data restored to a fall logic level (Vcc or Vss).
As mentioned above, a read or refresh operation must be performed on each row in the DRAM before the charge level on the storage node 106 falls below the critical level. Thus, it is important to make the pass transistor Q00 and storage capacitor C00 as ideal (i.e., have as little leakage) as possible. In addition, the critical charge level is dependent upon the capacitance of the storage capacitor C00: The larger the capacitance, the greater amount of charge that can be stored on the capacitor. Having more charge on the capacitor means that more charge can be lost before the total charge on the capacitor falls below the critical level. Thus, it is important to construct storage capacitors to have as large a capacitance as possible. While the capacitance of a DRAM cell storage capacitor can be increased by physically increasing the size of the storage cell, a drawback to such an approach is that the physical limitations of a DRAM cell layout that may place constraints on the size of the storage capacitor. Furthermore, increasing the size of the storage capacitor will result in a larger array size.
To better understand the physical constraints of conventional DRAM cells, a side cross sectional view of memory cell M00 is set forth in FIG. 2. The memory cell M00 is designated by the general reference character 200, and shown to include a pass transistor 202 and a storage capacitor 204 formed on a substrate 206. The pass transistor 202 couples the storage capacitor 204 to a bit line 208 in order to allow data to be read from, written to, or refreshed within, the memory cell 200.
The storage capacitor 204 includes a storage node 210 and a top plate 212 separated by a capacitor dielectric 214. The storage node 210 is formed from polysilicon and is coupled to the pass transistor 202. The capacitor dielectric 214 may be a silicon dioxide or a silicon dioxide-silicon nitride-silicon dioxide (SiO2xe2x80x94Si3N4xe2x80x94SiO2) combination. The top plate 212 is formed from polysilicon, and all storage cells on the DRAM array may share the same top plate 212. The top plate 212 may be maintained at a xe2x80x9cplatexe2x80x9d voltage having a potential equivalent to Vcc/2 in order to reduce the electric field across the capacitor dielectric 214.
The capacitance of the storage capacitor 204 is determined by the surface area of the storage node 210, the dielectric constant of the capacitor dielectric 214, and the thickness of the capacitor dielectric 214 (the distance between the top plate 212 and the storage node 210).
The pass transistor 202 is shown to include a source region 216 and a drain region 218 formed within the substrate 206. The substrate 206 is P-type doped silicon and the source region 216 and drain region 218 are N-type doped silicon. The P-N junction created between the substrate 206 and the source and drain regions (216 and 218) generates a parasitic junction capacitance which limits the performance of the pass transistor 202. The pass transistor 202 also includes a control gate 220 placed between the source region 216 and drain region 218, and separated from the substrate 206 by a thin control dielectric 222. The control gate 220 is polysilicon, and the thin control dielectric 222 may be silicon dioxide, or a combination silicon dioxide-nitride layer.
The pass transistor 202 is coupled to the storage capacitor 204 via the drain region 218. The pass transistor 202 is further coupled to a bit line contact 224 via the source region 216. The contact 224 is coupled to the bit line 208. The bit line 208 is a metal, for example Al, or alternatively, a titanium-tungsten combination (TiW). Due to smaller device geometries, the depth of the source and drain regions (216 and 218) (i.e., distance the source and drain extend into the substrate) is correspondingly small. A drawback to shallower sources and drains (216 and 218) can result from metal contacts extending through the source and/or drain to the substrate. Such contact xe2x80x9cspikingxe2x80x9d can result in a Schottky-barrier type junction, instead of P-N junctions.
In operation, when the control gate 220 is at a voltage that is one Vtn above that of the source 216, a low impedance path is formed between the storage node 210 and the bit line 208. In this manner, data can be read from, written to, or restored at the storage node 210. However, if the control gate 220 voltage is less than a threshold voltage above the source region 216 and drain region 218, the pass transistor 202 forms a high impedance path between the storage capacitor 204 and the bit line 208. In this manner, a low voltage on the control gate 220 (such as Vss) results in the isolation of the bit line 208 from storage node 210, and only unwanted leakage mechanisms may interfere with the data integrity.
One type of unwanted leakage mechanism is current that leaks from the drain region 218 to the source region 216 of the pass transistor 202. This current is represented by the character xe2x80x9cIleakxe2x80x9d in FIG. 2. The current Ileak can be problematic, due to short channel effects resulting from a very short channel length. This raises a barrier to the limit to which transistor dimensions can be shrunk, which in turn, places a limitation on how small a DRAM array can be. Short channel effects will further effect the reliability of adjusting the threshold voltage of the pass transistor 202. Because the operation of the pass transistor 202 is dependent upon its threshold, it would be desirable to have greater control over the channel region of the pass transistor 202.
The control gate 220 runs the full length of the DRAM array in the row direction, forming the word line shown as WL0 in FIG. 1. Referring back to FIG. 1, each word line is shown to be coupled to the control gate of all the DRAM cells within its particular row. This arrangement results in a relatively large capacitive load on the word line. In order to reduce the speed required to drive the word line between high and low voltages, it is desirable to make the word line have as little resistance as possible. The polysilicon word line resistance may be reduced by forming a self-aligned silicide (salicide) structure on it Alternatively, a metal layer may run parallel to, and over the polysilicon, and be periodically connected to the polysilicon by way of contacts. Such a structure is often referred to as a xe2x80x9cstrappedxe2x80x9d word line.
As device geometries continue to shrink, it would be desirable to arrive at a DRAM memory cell that has small feature sizes (such as short channel lengths) but does not suffer from the short channel effects, parasitic capacitance, or susceptibility to junction spiking. At the same time, it is also desirable to retain a compact memory cell size.
According to the present invention, a dynamic random access memory (DRAM) cell includes a-pass transistor and a charge storage device. The pass transistor is formed on an epitaxially grown silicon mesa. The top surface of the silicon mesa includes an inset furrow which results in the silicon mesa having a narrow thickness portion below the inset furrow. The channel region of the pass transistor is formed at the narrow thickness portion. A control gate is formed adjacent to the channel region. The narrow thickness of the channel region provides greater control over the channel region, resulting in advantageous charge storage capabilities. In addition, the narrow thickness of the channel region allows for shorter channel dimensions, improving the density of DRAM arrays. The source and drain regions are formed in surrounding thicker portions of the silicon mesa. The thicker source and drain regions result in greater resistance to the adverse effects of contact spiking.
According to one aspect of the preferred embodiment, a control gate is formed above the channel region.
According to another aspect of the preferred embodiment, a control gate is formed below the channel region.
According to another aspect of the preferred embodiment, the pass transistor is a double-gate transistor having a bottom control gate formed below the channel region, and a top gate formed above the channel region.
An advantage of the present invention is that it provides a DRAM memory cell having small transistor dimensions that is not susceptible to the adverse effects of contact spiking.